SystemVerilog probes · 02Vivado: supported

module instance with no instance name: inv(sw[0], led[0]);

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2020.1 synthesis log of a public CS223 lab repo: its top module instantiates two submodules without instance names, and the log says 'INFO: [Synth 8-6155] done synthesizing module '<its top>' (3#1)' and 'Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.'; implementation: 'write_bitstream completed successfully'. Not in UG901; IEEE 1800 requires the name

What does the open-source chain do with it?

since #4 the instance is named in the compiler copy, with a note: 'design.sv:5: note [unnamed-instance]: named the instance: inv u_inv(sw[0], led[0]);' (the standard and Yosys need it; Vivado accepts both); all four stages pass

Which error pages explain the messages?

• unnamed-instance: `inv(sw[0], led[0]);`, an instance without a name: Vivado accepts it, the standard and yosys do not, so the CLI names it u_inv in a temporary compiler copy and says so. Your saved source stays unchanged.

What is the probe's code?

From test/sv/02_unnamed_inst.

design.sv

module inv(input logic a, output logic y);
  assign y = ~a;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  inv(sw[0], led[0]);          // instance without a name (seen in a CS223 lab that Vivado built)
  assign led[15:1] = sw[15:1];
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h1231; #1
    if (!(led === 16'h1230)) begin $display("FAIL: inverter output (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0000; #1
    if (!(led === 16'h0001)) begin $display("FAIL: inverter output (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: always_comb with an if and no else (a latch is inferred)
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