errors · bitdewfpga sim / bit, the source scan before the tools run

design.sv:5: note [unnamed-instance]: named the instance: inv u_inv(sw[0], led[0]); (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both)

Not an error: the build goes on using a temporary compiler copy. The CLI prints the normalized line without editing your saved source. A construct that cannot be normalized safely is still reported as an error.

design.sv:5: note [unnamed-instance]: named the instance:  inv u_inv(sw[0], led[0]);   (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both) https://nosey-dewdrop.github.io/dewfpga/errors/unnamed-instance/
design.sv:5: ERROR [unnamed-instance]: `inv(` is an instance without a name: Vivado lets that pass; the standard and Yosys do not. Fix: write  inv u_inv( https://nosey-dewdrop.github.io/dewfpga/errors/unnamed-instance/

Why does it happen?

IEEE 1800 requires an instance name between the module name and the port list; Vivado's parser is lenient, so a lab that built in Vivado can carry one.

What is the fix?

Nothing, when the note printed: the compiler copy has a name; your file is unchanged. To make the name explicit in your source, write:

inv u_inv(sw[0], led[0]);

Which command prints it?

• dewfpga sim
• dewfpga bit

Which probes in test/sv print this code?

• module instance with no instance name: inv(sw[0], led[0]);

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.