SystemVerilog probes · 01Vivado: supported

always_comb with an if and no else (a latch is inferred)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2020.1 synthesis log of a public CS223 lab repo: 'WARNING: [Synth 8-327] inferring latch for variable '<a register>'' in an always_comb, then 'Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.'; its implementation log: 'write_bitstream completed successfully'. UG901 v2023.2 Ch.5 'Latches' (p.84): 'Vivado synthesis issues a warning ... This warning lets you verify that the inferred Latch functionality was intended.'

What does the open-source chain do with it?

since #4; rtl: PASS; bit: 'design.sv:3: warning [latch]: latch inferred for q (an if without else in always_comb): q keeps its value when no branch assigns it; Vivado builds the latch too, with the same warning (UG901 Ch.5 Latches). Fix: if you meant a register, write always_ff with a clock; if a latch, always_latch; if neither, give q a value on every path (an else branch, or a default at the top of the block).'; bit: 'pnr ok: 0 LUT, 1 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048574 output bits compared, all equal'

Which error pages explain the messages?

• latch: A combinational block leaves a signal unassigned on some path, so it has to remember its value: a latch, built as Vivado builds it, with the same warning.

What is the probe's code?

From test/sv/01_latch_comb.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic q;
  always_comb begin
    if (sw[1]) q = sw[0];      // no else: q keeps its value -> latch
  end
  assign led[0] = q;
  assign led[15:1] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0003; #1
    if (!(led[0] === 1'b1)) begin $display("FAIL: open latch must pass sw[0]=1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0001; #1 sw = 16'h0000; #1
    if (!(led[0] === 1'b1)) begin $display("FAIL: closed latch must hold 1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0002; #1
    if (!(led[0] === 1'b0)) begin $display("FAIL: open latch must pass sw[0]=0 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0000; #1 sw = 16'h0001; #1
    if (!(led[0] === 1'b0)) begin $display("FAIL: closed latch must hold 0 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

next: module instance with no instance name: inv(sw[0], led[0]);