errors · bitdewfpga bit, yosys

design.sv:3: warning [latch]: latch inferred for q (an if without else in always_comb): q keeps its value when no branch assigns it; Vivado builds the latch too, with the same warning (UG901 Ch.5 Latches). Fix: if you meant a register, write always_ff with a clock; if a latch, always_latch; if neither, give q a value on every path (an else branch, or a default at the top of the block).

A warning: the build goes on, with a latch (an LDCE cell) as Vivado would build. When the block's first branch point is a case, the message says "a case without default" and "no item assigns it", and the fix names "a default: item".

design.sv:3: warning [latch]: latch inferred for q (an if without else in always_comb): q keeps its value when no branch assigns it; Vivado builds the latch too, with the same warning (UG901 Ch.5 Latches). Fix: if you meant a register, write always_ff with a clock; if a latch, always_latch; if neither, give q a value on every path (an else branch, or a default at the top of the block). https://nosey-dewdrop.github.io/dewfpga/errors/latch/

Why does it happen?

always_comb if (en) q = d; says nothing about q when en is 0, so q must hold: that is a latch. Almost always the intent was a register (always_ff @(posedge clk)) or a default.

What is the fix?

always_comb begin
  q = 1'b0;
  if (en) q = d;
end

Which command prints it?

Which probes in test/sv print this code?

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.