errors · bitdewfpga bit, yosys

design.sv:3: ERROR [async-reset-nonconst]: this always_ff has an asynchronous reset (posedge clk or posedge btnC), so on btnC's edge every signal it writes must get a constant; here q is loaded from sw. yosys emulates that with FFs and a mux, so the board would not do what the simulation showed. Fix: reset to a constant, and load sw with the clock, behind an input of your own (load): if (btnC) q <= 0; else if (load) q <= sw; else q <= q + 1;

Two shapes, two texts. The second comes from yosys' own line above it. When the first if tests the reset at the level its edge leaves (posedge rst with if (!rst)), the code is async-reset-polarity instead.

design.sv:3: ERROR [async-reset-nonconst]: this always_ff has an asynchronous reset (posedge clk or posedge btnC), so on btnC's edge every signal it writes must get a constant; here q is loaded from sw. yosys emulates that with FFs and a mux, so the board would not do what the simulation showed. Fix: reset to a constant, and load sw with the clock, behind an input of your own (load):  if (btnC) q <= 0; else if (load) q <= sw; else q <= q + 1; https://nosey-dewdrop.github.io/dewfpga/errors/async-reset-nonconst/
ERROR: Async reset \btnC yields non-constant value 4'mmmm for signal \d.
design.sv:3: ERROR [async-reset-nonconst]: this always_ff has an asynchronous reset (posedge btnC), so on btnC's edge every signal it writes must get a constant, and d does not: it is written after the if (btnC) ... else ..., or from a signal, so on the reset edge it would load a value no flip-flop on the chip can load. Fix: make the reset if the whole block, with a constant for every signal in its first branch:  if (btnC) begin q <= 0; d <= 0; end else begin q <= ...; d <= ...; end https://nosey-dewdrop.github.io/dewfpga/errors/async-reset-nonconst/

Why does it happen?

always_ff @(posedge clk, posedge btn) makes btn an asynchronous reset: the flip-flop's set/reset pin, which can only force a constant. if (btn) q <= sw; asks the chip to load sw on that pin. yosys emulates it with extra flip-flops and a mux (or a loop), Vivado refuses it outright.

What is the fix?

always_ff @(posedge clk, posedge btn)
  if (btn) q <= '0;
  else if (load) q <= sw;
  else q <= q + 1;

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• always_ff @(posedge clk or posedge btnC) if (btnC) q <= sw[3:0]; (async load from a signal)
• a button used as an async 'reset' that loads cnt+1 (the button-as-clock counter)
• an always_ff with an async reset and a statement after its if/else (d <= q; runs on the reset edge too)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.