errors · bitdewfpga bit, yosys
design.sv:3: ERROR [async-reset-polarity]: this always_ff is sensitive to posedge btnC, but its first if tests !btnC, so the reset branch runs while btnC is low and on btnC's rising edge the block takes the else branch, which loads q from sw: no flip-flop on the chip loads a signal on its reset edge (yosys emulates it with FFs and a mux, so the board would not do what the simulation showed). Fix: test btnC at the level its edge leaves it: if (btnC) q <= 0; else ...; or keep if (!btnC) and write negedge btnC in the sensitivity list.
Under the CLI's line, yosys-slang's own: it refuses the same block.
design.sv:3: ERROR [async-reset-polarity]: this always_ff is sensitive to posedge btnC, but its first if tests !btnC, so the reset branch runs while btnC is low and on btnC's rising edge the block takes the else branch, which loads q from sw: no flip-flop on the chip loads a signal on its reset edge (yosys emulates it with FFs and a mux, so the board would not do what the simulation showed). Fix: test btnC at the level its edge leaves it: if (btnC) q <= 0; else ...; or keep if (!btnC) and write negedge btnC in the sensitivity list. https://nosey-dewdrop.github.io/dewfpga/errors/async-reset-polarity/
yosys-slang: design.sv:4:9: error: polarity of condition doesn't match edge sensitivity
if (!btnC) q <= 4'd0;
^~~~~Why does it happen?
always_ff @(posedge clk or posedge btnC) wakes the block when btnC rises, and at that moment btnC is 1. if (!btnC) is then false, so the branch that runs on the reset edge is the else: q <= sw. A flip-flop's asynchronous pin can only force a constant, so no cell on the chip does this; yosys emulates it with extra flip-flops and a mux, and the board would not follow the simulation. The reset branch as written runs only on a clock edge while btnC is low: a synchronous reset with the wrong sense.
What is the fix?
Test the reset at the level its edge leaves it, or name the other edge:
always_ff @(posedge clk or posedge btnC)
if (btnC) q <= '0;
else q <= sw;