errors · bitdewfpga bit, yosys

design.sv:3: ERROR [dual-edge]: this always block is sensitive to both edges of clk (@(posedge clk or negedge clk)), so cnt would change on every edge: no flip-flop on the chip does that, and neither reader builds it. Fix: clock the block on one edge (always_ff @(posedge clk)); for twice the rate use a faster clock (the Basys3's is 100 MHz) or count on both phases with two registers.

ERROR: Multiple edge sensitive events found for this signal!
design.sv:3: ERROR [dual-edge]: this always block is sensitive to both edges of clk (@(posedge clk or negedge clk)), so cnt would change on every edge: no flip-flop on the chip does that, and neither reader builds it. Fix: clock the block on one edge (always_ff @(posedge clk)); for twice the rate use a faster clock (the Basys3's is 100 MHz) or count on both phases with two registers. https://nosey-dewdrop.github.io/dewfpga/errors/dual-edge/

Why does it happen?

A 7-series flip-flop clocks on one edge. Dual-edge registers simulate fine and exist on no FPGA; Vivado refuses them too.

What is the fix?

always_ff @(posedge clk) cnt <= cnt + 1;

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• always @(posedge clk or negedge clk) cnt <= cnt + 1;

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.