SystemVerilog probes · 71Vivado: supported

one whole unpacked array assigned to another in always_ff: b <= a;

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Array assignments: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:4: error: the type of the variable', and dewfpga sim goes on with 'design.sv:4: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: "the type of the variable 'a' doesn't match the context type." (design.sv:4); yosys builds it; netlist: testbench only, eqv.sh cannot compile the RTL with iverilog

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/71_array_copy.

design.sv

module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] a [0:3], b [0:3];
  always_comb for (int i = 0; i < 4; i++) a[i] = sw[4*i +: 4];
  always_ff @(posedge clk) b <= a;               // one whole unpacked array assigned to another
  assign led = {b[3], b[2], b[1], b[0]};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i; reg [15:0] last;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #2000000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .sw(sw), .led(led));
  initial begin
    for (i = 0; i < 4096; i = i + 1) begin
      sw = (i * 16'h9e37) ^ (i >> 3); last = sw; tick;
      sw = ~sw; #1
      if (!(led === last)) begin $display("FAIL: b <= a copies all four elements (led=%h want %h)", led, last); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: a wor and a wand net, two drivers each
next: a void function that returns through output arguments