SystemVerilog probes · 72Vivado: supported

a void function that returns through output arguments

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Return values and void functions: Supported', 'Static and Automatic function: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:2: error: Function tb.dut.split port hi is not an input port.', and dewfpga sim goes on with 'design.sv:2: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: 'Function tb.dut.split port hi is not an input port.' (design.sv:2); yosys builds it; netlist: testbench only, eqv.sh cannot compile the RTL with iverilog

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/72_void_func_outputs.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  function automatic void split(input logic [7:0] x, output logic [3:0] hi, output logic [3:0] lo);
    hi = x[7:4];
    lo = x[3:0];
  endfunction
  logic [3:0] h, l;
  always_comb begin
    split(sw[7:0], h, l);              // a void function that returns through output arguments
    led = {8'd0, l, h};
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {~i[7:0], i[7:0]}; #1
      if (!(led === {8'd0, sw[3:0], sw[7:4]})) begin $display("FAIL: split(x, hi, lo) (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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