SystemVerilog probes · 73Vivado: supported

an unpacked array as a function argument

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Arrays as arguments to subroutines: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:3: sorry: Subroutine ports with unpacked dimensions are not yet supported.', and dewfpga sim goes on with 'design.sv:3: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: 'sorry: Subroutine ports with unpacked dimensions are not yet supported.' (design.sv:3); yosys builds it; netlist: testbench only, eqv.sh cannot compile the RTL with iverilog

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/73_array_arg.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  typedef logic [3:0] quad_t [0:3];
  function automatic logic [5:0] sum4(input quad_t q);   // an unpacked array as a function argument
    sum4 = q[0] + q[1] + q[2] + q[3];
  endfunction
  quad_t v;
  always_comb begin
    for (int i = 0; i < 4; i++) v[i] = sw[4*i +: 4];
    led = {10'd0, sum4(v)};
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === {10'd0, 6'(sw[3:0] + sw[7:4] + sw[11:8] + sw[15:12])})) begin $display("FAIL: sum4 of the four nibbles (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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