SystemVerilog probes · 74Vivado: supported

a .v design file with bit and final as names (keywords in SystemVerilog, names in Verilog 2005)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 'Targeting SystemVerilog for a Specific File' (p.269): 'By default, the Vivado synthesis tool compiles *.v files with the Verilog 2005 syntax and *.sv files with the SystemVerilog syntax.'

What does the open-source chain do with it?

rtl: 'iverilog -g2012 -o top_sim design.v tb.sv': dewfpga sim compiles a .v through a Verilog-2005 keyword wrapper (begin_keywords 1364-2005), so bit and final are names and the testbench prints PASS; bit: 'pnr ok: 10 LUT, 0 FF'; netlist: the testbench prints PASS on the netlist, then 'EQV PASS: 1048576 output bits compared, all equal'. Until 8 Oct 2026 the netlist stage failed in the harness, not the product: test/sv/eqv.sh read the .v with read_verilog -sv, which refused bit on line 3, and listed no registers (4a's read_slang copy of eqv.sh failed the same way); eqv.sh now reads a .v as the product does, read_verilog without -sv for yosys and the 1364-2005 keyword wrapper for yosys-slang and iverilog

What is the probe's code?

From test/sv/74_verilog2005_file.

design.v

// a Verilog-2005 file (.v): bit and final are SystemVerilog keywords, ordinary names in Verilog
module top(input [15:0] sw, output [15:0] led);
  wire bit;
  wire [3:0] final;
  assign bit = sw[0] ^ sw[1];
  assign final = sw[7:4] + 4'd1;
  assign led = {11'b0, final, bit};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hc3, i[7:0]}; #1
      if (!(led === {11'd0, 4'(sw[7:4] + 4'd1), sw[0] ^ sw[1]})) begin $display("FAIL: final and bit (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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