SystemVerilog probes · 83Vivado: supported

$realtobits and $bitstoreal in localparams (a real turned into its IEEE 754 bits and back)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.240): '$bitstoreal: Supported', '$realtobits: Supported', '$rtoi: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:2: error: Unable to evaluate parameter B value', and dewfpga sim goes on with 'design.sv:2: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:2: error: Unable to evaluate parameter B value: $realtobits(2.50000)'; bit: 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/83_realtobits.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  localparam logic [63:0] B = $realtobits(2.5);                 // IEEE 754: 64'h4004_0000_0000_0000
  localparam real         R = $bitstoreal(64'h3FF8_0000_0000_0000);   // 1.5
  assign led = sw ^ B[63:48] ^ 16'($rtoi(R * 4.0));             // sw ^ 16'h4004 ^ 16'd6
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 256; i++) begin
      sw = {i[7:0], i[7:0]}; #1;
      if (led !== (sw ^ 16'h4002)) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

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