SystemVerilog probes · 84Vivado: supported

a repeat loop with a constant count in always_comb (count the switches that are up)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.238): 'repeat statements: Supported, but repeat value must be constant'

What does the open-source chain do with it?

dewfpga sim passes and prints iverilog's "A repeat statement cannot be synthesized in an always_comb process." (design.sv:5), which UG901 contradicts for a constant count; yosys builds it and the netlist matches the RTL

What is the probe's code?

From test/sv/84_repeat_const.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [7:0] x; logic [3:0] n;
  always_comb begin                       // how many of sw[7:0] are up
    x = sw[7:0]; n = '0;
    repeat (8) begin n = n + x[0]; x = x >> 1; end
  end
  assign led = {sw[15:8], 4'd0, n};
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, k, bad = 0; logic [3:0] want;
  initial begin
    for (i = 0; i < 256; i++) begin
      sw = {i[7:0] ^ 8'h5a, i[7:0]}; #1;
      want = 0; for (k = 0; k < 8; k++) want = want + sw[k];
      if (led !== {sw[15:8], 4'd0, want}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

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