SystemVerilog probes · 82Vivado: supported

file tasks left in a design module: $fopen, $fdisplay and $fwrite (a debug trace)

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.239): '$fdisplay: Ignored', '$fopen: Ignored', '$fwrite: Ignored', and 'Vivado synthesis ignores unsupported system tasks.'

What does the open-source chain do with it?

yosys: "Can't resolve function name `\$fopen'." (design.sv:6), with no fix; with $fopen gone, $fdisplay stops it the same way on its line 7, and with both gone, $fwrite (task names it cannot resolve, measured apart); iverilog simulates it and writes the trace

What is the probe's code?

From test/sv/82_file_tasks_in_design.

design.sv

module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] q = '0;
  always_ff @(posedge clk) q <= q + sw[3:0];
  assign led = {12'd0, q};
  integer fd;                                  // a debug trace left in the design
  initial fd = $fopen("trace.txt");
  always @(posedge clk) begin
    $fdisplay(fd, "q=%h", q);
    $fwrite(fd, "sw=%h\n", sw);
  end
endmodule

tb.sv

module tb;
  logic clk = 0; logic [15:0] sw = 0; logic [15:0] led;
  top dut(.clk(clk), .sw(sw), .led(led));
  integer i, bad = 0; logic [3:0] want = 0;
  initial begin
    for (i = 0; i < 64; i++) begin
      sw = $random;
      #5 clk = 1; #5 clk = 0;
      want = want + sw[3:0];
      if (led !== {12'd0, want}) begin bad++; if (bad < 4) $display("FAIL: cycle %0d led=%h want=%h", i, led, want); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 64", bad);
    $finish;
  end
endmodule

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