SystemVerilog probes · 88Vivado: supported

a class used for its static function, called as util::rev(sw[3:0]) (no object is made)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Class', 'Static class member and methods: Supported', 'Scope and resolution operator (::): Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:7: syntax error', and dewfpga sim goes on with 'design.sv:7: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:7: syntax error'; bit: 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/88_class_static.

design.sv

class util;                              // a class used only for its static function; no object is made
  static function logic [3:0] rev(logic [3:0] a);
    rev = {a[0], a[1], a[2], a[3]};
  endfunction
endclass
module top(input logic [15:0] sw, output logic [15:0] led);
  assign led = {sw[15:4], util::rev(sw[3:0])};
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 256; i++) begin
      sw = {i[7:0], i[7:0]}; #1;
      if (led !== {sw[15:4], sw[0], sw[1], sw[2], sw[3]}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

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