SystemVerilog probes · 87Vivado: supported

a config declaration next to the design: config cfg; design work.top; default liblist work; endconfig

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.239): 'configurations: Supported'; Ch.10 Table 27 (p.288): 'config statements: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/87_config.

design.sv

config cfg;                              // a configuration: which library each cell of the design comes from
  design work.top;
  default liblist work;
endconfig
module top(input logic [15:0] sw, output logic [15:0] led);
  assign led = {sw[7:0], sw[15:8]};
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 256; i++) begin
      sw = {i[7:0] ^ 8'h3c, i[7:0]}; #1;
      if (led !== {sw[7:0], sw[15:8]}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

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