SystemVerilog probes · 86Vivado: supported

an extern module declaration ahead of the module: extern module inv4(input logic [3:0] a, output logic [3:0] y);

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'External modules: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:1: syntax error', and dewfpga sim goes on with 'design.sv:1: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:1: syntax error'; bit: 'pnr ok: 4 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/86_extern_module.

design.sv

extern module inv4(input logic [3:0] a, output logic [3:0] y);   // the ports, declared ahead of the body
module inv4(input logic [3:0] a, output logic [3:0] y);
  assign y = ~a;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  inv4 u_inv (.a(sw[3:0]), .y(led[3:0]));
  assign led[15:4] = sw[15:4];
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 256; i++) begin
      sw = {i[7:0], i[7:0]}; #1;
      if (led !== {sw[15:4], ~sw[3:0]}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

previous: a bitstream cast to an unpacked array: q = quad_t'(sw[7:0]); with typedef logic [3:0] quad_t [0:1]
next: a config declaration next to the design: config cfg; design work.top; default liblist work; endconfig