errors · bitdewfpga sim / bit, the source scan before the tools run (or yosys)

design.sv:2: ERROR [package-file-not-given]: cfg_pkg::MAGIC names the package cfg_pkg, which is declared in pkg.svh, and the tools are not given that file (they read what dewfpga collected, every .sv and .v of the folder or of the project: design.sv; a .svh or .vh reaches them only through an `include, a file outside the folder or the project not at all): iverilog stops at a syntax error there; yosys would drop the import and build every name of cfg_pkg as an undriven 1-bit wire: x on the board. Fix: add `include "pkg.svh" as the first line of design.sv; or move the package into design.sv, above the module.

design.sv:2: ERROR [package-file-not-given]: cfg_pkg::MAGIC names the package cfg_pkg, which is declared in pkg.svh, and the tools are not given that file (they read what dewfpga collected, every .sv and .v of the folder or of the project: design.sv; a .svh or .vh reaches them only through an `include, a file outside the folder or the project not at all): iverilog stops at a syntax error there; yosys would drop the import and build every name of cfg_pkg as an undriven 1-bit wire: x on the board. Fix: add   `include "pkg.svh"   as the first line of design.sv; or move the package into design.sv, above the module. https://nosey-dewdrop.github.io/dewfpga/errors/package-file-not-given/

Why does it happen?

Vivado projects list the package file among the sources, in order. dewfpga hands the tools every .sv and .v of the folder (or of the Vivado project), a package in its own file first, so package cfg_pkg in pkg.sv is read before design.sv names it (a file that holds only an interface or typedefs is handed before the files that use its names, too). A .svh or .vh is a header: the tools see it only where a file `includes it, and a file in another folder is not collected at all. Named from such a file, the package is missing when the design is read: iverilog stops, and yosys would silently drop the import.

What is the fix?

`include "pkg.sv"

as the first line of the file that uses the package, or move the package into that file above the module.

Which command prints it?

• dewfpga sim
• dewfpga bit

Which probes in test/sv print this code?

• a package in its own file (pkg.sv), referenced as cfg_pkg::NAME

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.