SystemVerilog probes · 54Vivado: supported

a name used before its declaration: assign led[0] = stop; logic stop;

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2017.3 log of the course's own example project (kept in a public CS223 repo), launch_simulation: xvlog on a design file prints 'WARNING: [VRFC 10-756] identifier <a signal> is used before its declaration' five times, then 'Built simulation snapshot <the testbench>'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:2: error: Unable to bind wire/reg/memory', and dewfpga sim goes on with 'design.sv:2: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: "Unable to bind wire/reg/memory `stop'" (design.sv:2); yosys builds it; netlist: testbench only, eqv.sh cannot compile the RTL with iverilog

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/54_use_before_decl.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  assign led[0] = stop;          // used here, declared on the next line
  logic stop;
  assign stop = sw[0] & sw[1];
  assign led[15:1] = sw[15:1];
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === {sw[15:1], sw[0] & sw[1]})) begin $display("FAIL: a name used before its declaration (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: async reset ORed with a synchronous clear: always_ff @(posedge clk, posedge btnC) if (btnC || btnU) q <= 0;
next: a conditional between two values of one enum: next = sw[0] ? RUN : IDLE;