SystemVerilog probes · 48Vivado: unverified

iff event qualifier: always_ff @(posedge clk iff sw[15])

Vivado: unverified. The open-source chain: all four stages pass.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.10 Table 27 (p.286) lists 'Iff event qualifier: Supported' and, two rows below it, 'Conditional event controls: Not Supported'. IEEE 1800-2017 9.4.2.3, Conditional event controls, is the clause that defines @(... iff ...) (slang's table of LRM clauses names 9.4.2.3 so, and its test for it is the standard's always @(a iff enable == 1) example), so the guide contradicts itself. UG901 v2022.2 Table 8-1 (p.288) the same

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:3: syntax error', and dewfpga sim goes on with 'design.sv:3: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:3: syntax error'; bit: 'pnr ok: 0 LUT, 8 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/48_iff_event.

design.sv

module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  logic [7:0] q;
  always_ff @(posedge clk iff sw[15]) q <= sw[7:0];   // the edge counts only while sw[15] is 1
  assign led = {8'b0, q};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .sw(sw), .led(led));
  initial begin
    sw = 16'h80A5; tick;
    if (!(led === 16'h00A5)) begin $display("FAIL: sw[15]=1, q loads (led=%h)", led); $finish; end
    sw = 16'h003C; tick; tick;
    if (!(led === 16'h00A5)) begin $display("FAIL: sw[15]=0, q holds (led=%h)", led); $finish; end
    sw = 16'h803C; tick;
    if (!(led === 16'h003C)) begin $display("FAIL: sw[15]=1 again, q loads (led=%h)", led); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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