SystemVerilog probes · 47Vivado: supported

type parameter: module inv_t #(parameter type T = logic [3:0]), overridden with #(.T(logic [7:0]))

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Type parameters: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 12 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/47_type_param.

design.sv

module inv_t #(parameter type T = logic [3:0]) (input T a, output T y);
  assign y = ~a;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  inv_t #(.T(logic [7:0])) u8 (.a(sw[7:0]), .y(led[7:0]));     // the type overridden: 8 bits
  inv_t                    u4 (.a(sw[11:8]), .y(led[11:8]));   // the default type: 4 bits
  assign led[15:12] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === {4'd0, ~sw[11:8], ~sw[7:0]})) begin $display("FAIL: type parameter (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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