errors · bitdewfpga bit, nextpnr
design.sv:2: ERROR [internal-tristate]: a tri-state driver (a z, at design.sv:2) on a signal that is not an inout pin of the top module: the chip has tri-state buffers on its pins only. Vivado converts such a driver to logic (UG901 Ch.5 Tristates); yosys keeps it as a $_TBUF_ cell, and nextpnr has nothing to place it on. Not a size problem. Fix: select with a mux instead: assign bus = sel ? b : a; and keep z for an inout pin only.
nextpnr's own line first (no Bels remaining of type '$_TBUF_', which reads like a size problem); the CLI names the real cause and the line with the z.
ERROR: Unable to place cell '$auto$simplemap.cc:331:simplemap_tribuf$1519', no Bels remaining of type '$_TBUF_'
design.sv:2: ERROR [internal-tristate]: a tri-state driver (a z, at design.sv:2) on a signal that is not an inout pin of the top module: the chip has tri-state buffers on its pins only. Vivado converts such a driver to logic (UG901 Ch.5 Tristates); yosys keeps it as a $_TBUF_ cell, and nextpnr has nothing to place it on. Not a size problem. Fix: select with a mux instead: assign bus = sel ? b : a; and keep z for an inout pin only. https://nosey-dewdrop.github.io/dewfpga/errors/internal-tristate/Why does it happen?
assign bus = sel ? a : 'z; on an internal wire describes a shared bus; a 7-series chip has no internal tri-state, Vivado rewrites it as a mux (UG901 Ch.5 Tristates), yosys does not.
What is the fix?
assign bus = sel ? b : a;Which command prints it?
Which probes in test/sv print this code?
- the textbook's tristate buffer module (assign y = en ? a : 4'bz) instantiated four times, each driving one nibble of an output tri [15:0] port
- an internal tri bus with two tristate drivers taking turns (the textbook's mux from tristate buffers)
Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.