errors · bitdewfpga bit, yosys

design.sv:3: ERROR [async-reset-not-alone]: this always block is sensitive to two edges (@(posedge clk, posedge btnC)), so one of them is an asynchronous reset, but its first if does not test that reset alone (a reset ORed with a synchronous clear: if (rst || clear)), so neither reader can tell the reset from the clock. Fix: test the reset alone first and put the synchronous clear in the else: if (btnC) q <= 0; else if (clear) q <= 0; else q <= q + 1;

yosys' own line comes first; the CLI reads which block it was and names the cause.

ERROR: Multiple edge sensitive events found for this signal!
design.sv:3: ERROR [async-reset-not-alone]: this always block is sensitive to two edges (@(posedge clk, posedge btnC)), so one of them is an asynchronous reset, but its first if does not test that reset alone (a reset ORed with a synchronous clear: if (rst || clear)), so neither reader can tell the reset from the clock. Fix: test the reset alone first and put the synchronous clear in the else:  if (btnC) q <= 0; else if (clear) q <= 0; else q <= q + 1; https://nosey-dewdrop.github.io/dewfpga/errors/async-reset-not-alone/

Why does it happen?

The reader pairs the second edge in the list with the first if of the block; if (btnC || btnU) names two signals, and only one of them is in the list, so the pattern does not match and neither reader can build the flip-flop.

What is the fix?

if (btnC) q <= '0;
else if (btnU) q <= '0;
else q <= q + 1;

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• async reset ORed with a synchronous clear: always_ff @(posedge clk, posedge btnC) if (btnC || btnU) q <= 0;

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.