errors · bitdewfpga bit, yosys
design.sv:3 and design.sv:4: warning [tristate-to-logic]: bus has two tri-state drivers (a z, at design.sv:3 and design.sv:4) and is not an inout pin of the top module: the chip has tri-state buffers on its pins only, so yosys built the two drivers as logic, as Vivado does (UG901 Ch.5 Tristates). On the board bus is never z: with no driver on it shows one driver's value, with both on the other's, where the simulation shows z and x. Fix: select with a mux instead, so the simulation shows what the board does: assign bus = sel ? b : a; and keep z for an inout pin only.
A warning, not an error: the bitstream is built. yosys' own lines first (multiple conflicting drivers, one per bit, which reads like the two-always-blocks error); the CLI names the two lines with the z and what the board shows instead of z.
Warning: multiple conflicting drivers for top.\bus [0]:
port Y[0] of cell $1 ($tribuf)
port Y[0] of cell $0 ($tribuf)
design.sv:3 and design.sv:4: warning [tristate-to-logic]: bus has two tri-state drivers (a z, at design.sv:3 and design.sv:4) and is not an inout pin of the top module: the chip has tri-state buffers on its pins only, so yosys built the two drivers as logic, as Vivado does (UG901 Ch.5 Tristates). On the board bus is never z: with no driver on it shows one driver's value, with both on the other's, where the simulation shows z and x. Fix: select with a mux instead, so the simulation shows what the board does: assign bus = sel ? b : a; and keep z for an inout pin only. https://nosey-dewdrop.github.io/dewfpga/errors/tristate-to-logic/Why does it happen?
assign bus = en_a ? a : 'z; assign bus = en_b ? b : 'z; in one module describes a shared bus. A 7-series chip has tri-state buffers on its pins only, so Vivado rewrites the two drivers as logic (UG901 Ch.5 Tristates), and synth_xilinx does the same (tribuf -logic). The simulation shows z with no driver enabled and x with both; the board shows a value. (A z driver behind a submodule port is kept as a cell nextpnr cannot place: internal-tristate.)
What is the fix?
assign bus = sel ? b : a;