errors · simdewfpga sim, the source scan before iverilog runs
tb.sv:1: ERROR [included-twice]: tb.sv `includes pkg.sv, and the simulator reads pkg.sv with the design already (dewfpga hands every .sv and .v of the folder to the simulator, a package file first: pkg.sv design.sv): read a second time, package cfg_pkg is declared twice and iverilog stops at its first line ('syntax error', 'I give up'). Fix: delete the `include "pkg.sv" line from tb.sv; cfg_pkg reaches the testbench through the design, which iverilog reads first.
tb.sv:1: ERROR [included-twice]: tb.sv `includes pkg.sv, and the simulator reads pkg.sv with the design already (dewfpga hands every .sv and .v of the folder to the simulator, a package file first: pkg.sv design.sv): read a second time, package cfg_pkg is declared twice and iverilog stops at its first line ('syntax error', 'I give up'). Fix: delete the `include "pkg.sv" line from tb.sv; cfg_pkg reaches the testbench through the design, which iverilog reads first. https://nosey-dewdrop.github.io/dewfpga/errors/included-twice/Why does it happen?
iverilog reads the files in one stream: the design's files first (every .sv and .v of the folder, a package file before the files that use it), then the testbench. A package file the testbench includes is read a second time there, and a package declared twice is a syntax error to iverilog (measured: ./pkg.sv:1: syntax error, I give up.). The same happens when the design includes pkg.sv and the testbench includes it too. The build never reads the testbench, so what it includes does not change which files the build is given.
What is the fix?
Delete the include line from the testbench. The package is already in the simulation through the design, read before the testbench, so cfg_pkg::MAGIC in the testbench resolves without it. A header of macros (defs.svhwith onlydefine lines) may stay included in both: it declares nothing twice, and this check names only a file the design's list holds, or a package file the design `includes.