errors · bitdewfpga bit, synthesis, before yosys reads the design
design.sv:3: note [fsm-encoding-kept]: (* fsm_encoding = "one_hot" *) on state is not applied: the netlist keeps the 2-bit codes the declaration gives state, so its power-up (every flip-flop at 0, as the board starts a register without a start value) is the state with code 0, the one dewfpga sim starts in; re-encoded, the flip-flops would start in no state until the first reset (the netlist and the board would sit dark where the simulation moved on). Vivado applies the attribute (UG901 FSM_ENCODING), and the guide does not say what its re-encoded register holds before the first reset. Fix: none needed for this board, and the attribute may stay for Vivado; to start state in a state other than the one with code 0, give it a start value in its declaration (state_t state = RUN;), which every tool honours.
dewfpga bit on a three-state machine whose register carries the attribute ((* fsm_encoding = "one_hot" *) logic [1:0] state; on line 3, IDLE = 0, RUN = 1, DONE = 2, a synchronous reset to IDLE, no start value):
design.sv:3: note [fsm-encoding-kept]: (* fsm_encoding = "one_hot" *) on state is not applied: the netlist keeps the 2-bit codes the declaration gives state, so its power-up (every flip-flop at 0, as the board starts a register without a start value) is the state with code 0, the one dewfpga sim starts in; re-encoded, the flip-flops would start in no state until the first reset (the netlist and the board would sit dark where the simulation moved on). Vivado applies the attribute (UG901 FSM_ENCODING), and the guide does not say what its re-encoded register holds before the first reset. Fix: none needed for this board, and the attribute may stay for Vivado; to start state in a state other than the one with code 0, give it a start value in its declaration (state_t state = RUN;), which every tool honours. https://nosey-dewdrop.github.io/dewfpga/errors/fsm-encoding-kept/
xdc ok: 34 ports, all mapped, 71 unused pins in the XDC ignored.
note [no-create-clock]: no create_clock in Basys3_Master.xdc; timing is checked against the Basys3's 100 MHz oscillator (--freq 100). https://nosey-dewdrop.github.io/dewfpga/errors/no-create-clock/
pnr ok: 3 LUT, 2 FF, clk 624.22 MHz (PASS at 100.00 MHz) (full log: top.log)
top.bit 2.2 MBBefore #35 the same design built without a note, as pnr ok: 3 LUT, 3 FF, clk 645.58 MHz (PASS at 100.00 MHz): three flip-flops for a two-bit register.
Why does it happen?
yosys' fsm pass, which runs inside synth_xilinx, finds a register that behaves as a state machine and re-encodes it: the two-bit state above became three one-hot flip-flops, with or without the attribute (the attribute asks for exactly that, and auto would have given the same). Every flip-flop without a start value powers up at 0 on the board, and since #34 in the netlist too, so the re-encoded register powered up as 000, which is none of the three one-hot states: with no reset pressed the machine sat there on every clock, and led stayed dark where the student's simulation, starting in IDLE, showed RUN after the first edge. Measured on the design above with the testbench of its probe: the netlist of before #35 printed FAIL: after first edge no reset led=0000000000000000 expected all on (RUN), and its three FDRE all carried INIT(1'h0).
So the build now sets fsm_encoding = "none" on every named wire of the design before synth_xilinx reads it, which fsm_detect honours (yosys: help fsm_detect), and the register keeps the codes its declaration gives it: two flip-flops, 00 is IDLE, and the netlist moves to RUN at the first edge as dewfpga sim does (PASS from the same testbench, 2 FDRE, both INIT(1'h0)). A student's own attribute is replaced like every other wire's, and the note names its line: left in place it kept yosys' recoding, and an init attribute beside it does not give the recoded register a start (yosys: "Initialization value on FSM state register is ignored"), so the only netlist whose power-up is a state is the one with the student's codes. The note is printed for a register only (the Q of a flip-flop in the design as yosys reads it); a combinational variable that shares the declaration (state_t state, next;) gets the none silently. The blink template's FASM is byte for byte the one before this change: nothing in it is a state machine to yosys.
What differs from Vivado?
Vivado applies FSM_ENCODING (UG901 Ch.2, "FSM_ENCODING": one_hot, sequential, johnson, gray, auto, none), and re-encodes by default (auto). What its re-encoded register holds before the first reset is not in the guide, so whether a Vivado bitstream of the same design sits in no state until the reset button is pressed is not stated here: the values on this page are the open chain's, measured on its own netlist.
What is the fix?
None for this board: the note says what the build did, and the attribute may stay in the file for Vivado. To start the machine in a state other than the one with code 0, every tool honours a start value in the declaration (UG901 v2022.2 Ch.4 p.79):
(* fsm_encoding = "one_hot" *) logic [1:0] state = RUN;A press of the reset button puts the register in its reset state in every tool alike.