errors · bitdewfpga bit, before place and route

note [no-create-clock]: no create_clock in Basys3_Master.xdc; timing is checked against the Basys3's 100 MHz oscillator (--freq 100).

note [no-create-clock]: no create_clock in Basys3_Master.xdc; timing is checked against the Basys3's 100 MHz oscillator (--freq 100). https://nosey-dewdrop.github.io/dewfpga/errors/no-create-clock/

Why does it happen?

The course's master XDC ships with its create_clock line commented out. Without it nextpnr would check nothing; the CLI asks for 100 MHz, the oscillator's rate, so a design that cannot keep up is caught (timing-not-met).

What is the fix?

Nothing, or uncomment the clock line for a clock of your own period:

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• a clock divider's output clocks more logic than 100 MHz allows (four decimal digits of a 14-bit value on the slow clock); the XDC has no create_clock, as the course's master XDC arrives

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.