errors · bitdewfpga bit, nextpnr
ERROR [design-too-big]: the design does not fit the XC7A35T (no SLICE_LUTX left: 20800 LUTs, 41600 FFs; a memory is built from LUTs as distributed RAM, unless (* ram_style = "block" *) asks for a block RAM). The counts are in top.log. Fix: make it smaller: fewer bits, a smaller memory, one divider or multiplier shared over several cycles.
ERROR: Unable to place cell '$abc$1234$auto$blifparse.cc:396:parse_blif$5678', no Bels remaining of type 'SLICE_LUTX'
ERROR [design-too-big]: the design does not fit the XC7A35T (no SLICE_LUTX left: 20800 LUTs, 41600 FFs; a memory is built from LUTs as distributed RAM, unless (* ram_style = "block" *) asks for a block RAM). The counts are in top.log. Fix: make it smaller: fewer bits, a smaller memory, one divider or multiplier shared over several cycles. https://nosey-dewdrop.github.io/dewfpga/errors/design-too-big/Why does it happen?
The Basys3's chip has 20800 LUTs and 41600 flip-flops. A large memory without ram_style = "block" is built from LUTs; a wide divider or multiplier in one cycle takes thousands. A cell type that is not a chip resource is one of internal-tristate, wired-net, power-operator or empty-module, named as such.
What is the fix?
top.log lists the counts per cell type. Ask for a block RAM, narrow the data, share the operator over cycles.
(* ram_style = "block" *) logic [7:0] mem [0:4095];