errors · bitdewfpga bit, yosys
design.sv:4 and design.sv:6: ERROR [always-and-assign]: q is written by an always block (design.sv:4) and by a continuous assign (design.sv:6): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive q from one of them.
design.sv:4 and design.sv:6: ERROR [always-and-assign]: q is written by an always block (design.sv:4) and by a continuous assign (design.sv:6): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive q from one of them. https://nosey-dewdrop.github.io/dewfpga/errors/always-and-assign/Why does it happen?
assign is a permanent driver; the always block is another. yosys resolves the conflict to a constant with a warning, and the netlist no longer matches the RTL.
What is the fix?
Keep one: register it in the always block, or make it a wire with the assign.
assign q = d & en;