errors · simdewfpga sim, vvp
ERROR [sim-exit]: the simulator stopped with exit 1 (its message is above: a $fatal, or a testbench that ends without $finish). Fix: read the line above this one and fix what it names; make the testbench end with $finish.
FATAL: blink_tb.sv:35: stopped on purpose
Time: 200000 Scope: blink_tb
ERROR [sim-exit]: the simulator stopped with exit 1 (its message is above: a $fatal, or a testbench that ends without $finish). Fix: read the line above this one and fix what it names; make the testbench end with $finish. https://nosey-dewdrop.github.io/dewfpga/errors/sim-exit/Why does it happen?
$fatal ends the simulation with an error exit on purpose: the testbench found something it cannot continue from. The line before this one is its message.
What is the fix?
Fix what the $fatal line names in the design, or the check if its expectation is wrong; a check that should only be reported uses $error and lets the run end with $finish.
if (led !== expected) $error("led is %h, expected %h", led, expected);