errors · simdewfpga sim, before iverilog
ERROR [no-testbench]: no testbench for blink in this folder: a testbench is a module without ports that instantiates blink and ends with $finish; blink_tb.sv is the usual name. Fix: write one next to the design; 'dewfpga new blink' gives an example (blink/blink_tb.sv).
ERROR [no-testbench]: no testbench for blink in this folder: a testbench is a module without ports that instantiates blink and ends with $finish; blink_tb.sv is the usual name. Fix: write one next to the design; 'dewfpga new blink' gives an example (blink/blink_tb.sv). https://nosey-dewdrop.github.io/dewfpga/errors/no-testbench/Why does it happen?
The CLI finds the testbench by its content, not its name: a module with no ports that instantiates the design. A testbench with ports, or one for another module, is not it.
What is the fix?
Write blink_tb.sv next to the design: a module with no ports, an instance of blink, a clock, checks with $error, and $finish at the end. dewfpga new blink gives one to copy from.
dewfpga new example && cat example/blink_tb.sv