errors · simdewfpga sim, vvp
ERROR [sim-timeout]: the simulation did not finish in 120 s: the testbench never reached $finish (a free-running clock never stops on its own). Fix: end the testbench with $finish; SIM_TIMEOUT=600 dewfpga sim waits longer.
ERROR [sim-timeout]: the simulation did not finish in 120 s: the testbench never reached $finish (a free-running clock never stops on its own). Fix: end the testbench with $finish; SIM_TIMEOUT=600 dewfpga sim waits longer. https://nosey-dewdrop.github.io/dewfpga/errors/sim-timeout/Why does it happen?
An always #5 clk = ~clk; runs forever; only $finish ends the run. A testbench that waits for a condition the design never reaches (a counter to 50 million at 100 MHz takes a long simulated second) hits the timeout too.
What is the fix?
End the testbench with $finish, and shorten long waits (a smaller parameter for the count in simulation). More time when it is really needed:
SIM_TIMEOUT=600 dewfpga sim