errors · bitdewfpga sim / bit, the source scan before the tools run
blink_tb.sv:6: ERROR [top-is-a-testbench]: blink_tb is a testbench (it has no ports), not a design. Fix: name a design module instead: dewfpga bit blink.
blink_tb.sv:6: ERROR [top-is-a-testbench]: blink_tb is a testbench (it has no ports), not a design. Fix: name a design module instead: dewfpga bit blink. https://nosey-dewdrop.github.io/dewfpga/errors/top-is-a-testbench/Why does it happen?
A module without ports has nothing to connect to a pin; the CLI treats it as a testbench for the design it instantiates.
What is the fix?
dewfpga bit blink