cli · runrun one file, automatic standard pins

dewfpga run

What does its help text say?

dewfpga run <file.sv>           compile this file and load Basys3 (standard pins automatic; --build-only skips USB)

From dewfpga --help, as bin/dewfpga prints it.

What does the README say?

Save a .sv file anywhere and open it in VS Code. Click ▶ Run on Basys3 in the editor's upper-right corner. Connect the board through its PROG USB port and turn it on. No project folder, tasks file or pin file is needed for standard Basys3 IO. If the button is missing, run dewfpga vscode once and reload VS Code.

The four switches now control the four LEDs. Change sw to ~sw and Run again: the LED behavior inverts. Other editors can use the same CLI:

dewfpga run ~/Desktop/my_design.sv
dewfpga run ~/Desktop/my_design.sv --build-only  # no board needed

Run reads the chosen file and the modules it uses from the other .sv/.v files of its folder (with the package files they name), never a file the design does not use. Run on a submodule's file builds the one top that uses it. Inside a Vivado project, Run builds the project: its files, its top, its .xdc. Literal include/data paths must be relative, without spaces or ... dewfpga sim runs a separate testbench. Short setup guide.

From the README.

Which errors can it stop with?

2 codes in the error catalog.

• explicit-port: Not an error: a port list in Vivado's netlist form names a port with an expression, .dp(\<const0> ), which Vivado builds and yosys' reader does not; the copy the tools read writes it as a plain port.
• module-without-endmodule: A module's endmodule is missing or misspelled, so the module never ends; the scan stops here instead of naming the wrong top.

Which patch notes name it?

• An empty folder in VS Code, and a misspelled endmodule
• Run shows its error, reads the lab folder, and prints only what a student acts on
• Run builds every lab folder the folder command builds

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