errors · bitdewfpga bit, yosys

design.sv:3: ERROR [initial-from-signal]: `num = sw` here is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8), and the chip has no power-up value that follows a signal, so yosys stops. Fix: for a wire write assign num = sw; for a register give num a constant start value (logic [15:0] num = '0;) and load sw with the clock (if (btnC) num <= sw;).

ERROR: Failed to get a constant init value for \num: \sw
design.sv:3: ERROR [initial-from-signal]: `num = sw` here is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8), and the chip has no power-up value that follows a signal, so yosys stops. Fix: for a wire write  assign num = sw;  for a register give num a constant start value (logic [15:0] num = '0;) and load sw with the clock (if (btnC) num <= sw;). https://nosey-dewdrop.github.io/dewfpga/errors/initial-from-signal/

Why does it happen?

initial num = sw; is evaluated once at time 0 in simulation. On the chip a register's start value is written into the bitstream, a constant; nothing can follow sw.

What is the fix?

assign num = sw;

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• an initial block that reads a signal: initial num = sw; (seen in a CS223 lab)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.