SystemVerilog probes · 77Vivado: unverified

an initial block that reads a signal: initial num = sw; (seen in a CS223 lab)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 does not say what Vivado does with an initial block that reads a signal: Ch.9 (p.251) says 'initial blocks are ignored during synthesis', and 'Initial Values' (p.244) says an initial value 'Is a constant.'. No Vivado log of this case in the corpus

What does the open-source chain do with it?

since #5; rtl: PASS; yosys: 'ERROR: Failed to get a constant init value for \num: \sw', then the CLI names the line and the fix (before #5 there was neither): 'design.sv:3: ERROR [initial-from-signal]:' 'here is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8), and the chip has no power-up value that follows a signal, so yosys stops. Fix: for a wire write assign num = sw; for a register give num a constant start value'; yosys-slang: 'design.sv:3:17: error: reading net state during design initialization unsupported'

Which error pages explain the messages?

• initial-from-signal: An initial block, or a declaration, sets a register's start value from a signal; power-up values are constants.

What is the probe's code?

From test/sv/77_initial_from_signal.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [15:0] num;
  initial num = sw;                          // a start value read from the switches
  always_ff @(posedge clk)
    if (btnC) num <= sw;
    else      num <= num + 16'd1;
  assign led = num;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i, k;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #2000000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    for (i = 0; i < 64; i = i + 1) begin
      sw = (i * 16'h2f5b) ^ 16'hffc0; btnC = 1'b1; tick; btnC = 1'b0;
      if (!(led === sw)) begin $display("FAIL: btnC loads sw (led=%h sw=%h)", led, sw); $finish; end
      for (k = 1; k <= 3; k = k + 1) begin
        tick;
        if (!(led === 16'(sw + k))) begin $display("FAIL: counts up from sw (led=%h want %h)", led, 16'(sw + k)); $finish; end
      end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: names the standard declares implicitly: a net from a port connection (.y(w)) and one from the left of an assign (assign eq = ...)
next: (* keep_hierarchy = "yes" *) on a module, spaced as in UG901