SystemVerilog probes · 76Vivado: supported

names the standard declares implicitly: a net from a port connection (.y(w)) and one from the left of an assign (assign eq = ...)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2021.2 logs of a public lab repo (CS-224, the course after CS223): a signal never declared and assigned only on the left of a continuous assignment, 'INFO: [Synth 8-6155] done synthesizing module '<that module>' (20#1)', 'Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.'; implementation 'write_bitstream completed successfully'. IEEE 1800-2017 6.10: an undeclared name in a port connection or on the left of a continuous assignment is an implicit net

What does the open-source chain do with it?

yosys warns 'Identifier `\w' is implicitly declared.' (design.sv:5) and the same for eq (design.sv:6), and builds it right

What is the probe's code?

From test/sv/76_implicit_net.

design.sv

module and2(input logic a, b, output logic y);
  assign y = a & b;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  and2 u1 (.a(sw[0]), .b(sw[1]), .y(w));      // w is never declared: an implicit net from a port connection
  assign eq = sw[3:2] == sw[5:4];              // eq is never declared: an implicit net from the left of an assign
  assign led = {14'd0, eq, w};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 64; i = i + 1) begin
      sw = {10'h155, i[5:0]}; #1
      if (!(led === {14'd0, sw[3:2] == sw[5:4], sw[0] & sw[1]})) begin $display("FAIL: w and eq (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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