SystemVerilog probes · 78Vivado: supported

(* keep_hierarchy = "yes" *) on a module, spaced as in UG901

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.3 'KEEP_HIERARCHY Verilog Example' (p.60): '(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);'

What does the open-source chain do with it?

since #4; rtl: PASS; bit: 'pnr ok: 1 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/78_keep_hierarchy.

design.sv

(* keep_hierarchy = "yes" *) module inv(input logic a, output logic y);   // UG901 p.60, spaced as there
  assign y = ~a;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  inv u0 (.a(sw[0]), .y(led[0]));
  assign led[15:1] = sw[15:1];
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 16; i = i + 1) begin
      sw = {i[3:0], 11'h2a5, i[0]}; #1
      if (!(led === {sw[15:1], ~sw[0]})) begin $display("FAIL: inv kept as its own module (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: an initial block that reads a signal: initial num = sw; (seen in a CS223 lab)
next: the same attribute written without spaces: (*keep_hierarchy="yes"*) (yosys keeps the submodule)