errors · bitdewfpga sim / bit, the source scan before the tools run

design.sv:6: ERROR [finish-in-design]: $finish in a design module (top): Vivado ignores it (UG901 Table 21: $finish Ignored) and yosys stops on it. Fix: remove it, move the check to the testbench, or wrap it in `ifndef SYNTHESIS ... `endif.

design.sv:6: ERROR [finish-in-design]: $finish in a design module (top): Vivado ignores it (UG901 Table 21: $finish Ignored) and yosys stops on it. Fix: remove it, move the check to the testbench, or wrap it in `ifndef SYNTHESIS ... `endif. https://nosey-dewdrop.github.io/dewfpga/errors/finish-in-design/

Why does it happen?

$finish ends a simulation; a chip does not end. Vivado lists it as ignored in synthesis (UG901 Table 21); yosys refuses it. A check that stops the simulation belongs in the testbench.

What is the fix?

Move the check to the testbench, or hide it from synthesis (yosys and Vivado both define SYNTHESIS):

`ifndef SYNTHESIS
  if (done) $finish;
`endif

Which command prints it?

Which probes in test/sv print this code?

a design module that calls $finish in a simulation check (always @(posedge clk) if (...) $finish;), its submodule's ports named as the XDC's (counter.sv)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.