errors · bitdewfpga sim / bit, the source scan before the tools run
leftover_func_synth.v:2: ERROR [vivado-netlist-in-folder]: leftover_func_synth.v is a netlist Vivado wrote after synthesis, not source code (its header says so, and Yosys cannot read it); Vivado writes these under .sim/ and .runs/. Fix: delete it from this folder and keep your own .sv files.
leftover_func_synth.v:2: ERROR [vivado-netlist-in-folder]: leftover_func_synth.v is a netlist Vivado wrote after synthesis, not source code (its header says so, and Yosys cannot read it); Vivado writes these under .sim/ and .runs/. Fix: delete it from this folder and keep your own .sv files. https://nosey-dewdrop.github.io/dewfpga/errors/vivado-netlist-in-folder/Why does it happen?
Vivado writes <top>_func_synth.v (write_verilog -mode funcsim, marked NotValidForBitStream) under the project's .sim/ folder; a folder copied whole brings it along, and the CLI reads every .v in the folder.
What is the fix?
rm *_func_synth.v *_time_synth.v