errors · bitdewfpga bit, yosys
design.sv:3: ERROR [latch-loop]: latch inferred for q (an if without else in always_comb), and yosys built it as a LUT feedback loop, not a latch, so the board would not do what the simulation showed; Vivado builds an LDCE latch here, with a warning (UG901 Ch.5 Latches). Fix: give q a value on every path (an else branch, or a default at the top of the block); if you meant a latch, write always_latch instead of always_comb (both readers build that as a latch).
design.sv:3: ERROR [latch-loop]: latch inferred for q (an if without else in always_comb), and yosys built it as a LUT feedback loop, not a latch, so the board would not do what the simulation showed; Vivado builds an LDCE latch here, with a warning (UG901 Ch.5 Latches). Fix: give q a value on every path (an else branch, or a default at the top of the block); if you meant a latch, write always_latch instead of always_comb (both readers build that as a latch). https://nosey-dewdrop.github.io/dewfpga/errors/latch-loop/Why does it happen?
Since #4 the CLI makes yosys build an inferred latch as Vivado does (the latch warning). When the netlist still holds the value in a loop of LUTs instead of a latch cell (a shape the readers keep as logic), the board would glitch, so this is an error.
What is the fix?
Assign the signal on every path, or say latch when you mean it:
always_latch if (en) q <= d;