errors · bitdewfpga sim / bit, the source scan before the tools run

counter.sv:4: ERROR [two-tops]: 2 modules could be the top (nothing instantiates them): counter (counter.sv:4), top (counter.sv:8). Fix: name it: dewfpga bit counter

Both dewfpga sim and dewfpga bit stop before make; each names its own command in the fix.

counter.sv:4: ERROR [two-tops]: 2 modules could be the top (nothing instantiates them): counter (counter.sv:4), top (counter.sv:8). Fix: name it:  dewfpga bit counter https://nosey-dewdrop.github.io/dewfpga/errors/two-tops/

Why does it happen?

The top is the one design module nothing instantiates. Two of them (an old version kept in the file, two labs in one folder) and the CLI will not guess; a .xdc named after one of them decides it, and the CLI says so (top module: top (named by top.xdc)).

What is the fix?

Name the module, or name the pin file after it:

dewfpga bit counter

Which command prints it?

• dewfpga sim
• dewfpga bit

Which probes in test/sv print this code?

• two modules nothing instantiates, in one file named after one of them (counter.sv: the plain counter, and the board version the project names as its top)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.