SystemVerilog probes · 93Vivado: supported

two modules nothing instantiates, in one file named after one of them (counter.sv: the plain counter, and the board version the project names as its top)

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. Vivado logs of two public CS223 Lab 4 projects (Vivado 2015.2), each with one .sv file named after its plain counter and holding a board version next to it: the project's .xpr 'TopModule' and its runme.log 'synth_design -top <the board version>', 'Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.', a .bit written. Vivado builds the top the project names, whatever the file is called

What does the open-source chain do with it?

the scanner never picks a top by file name any more: dewfpga sim and dewfpga bit both stop with 'counter.sv:4: ERROR [two-tops]: 2 modules could be the top (nothing instantiates them): counter (counter.sv:4), top (counter.sv:8). Fix: name it: dewfpga bit counter' (sim says 'dewfpga sim counter'); no counter.bit. With a top.xdc in the folder the CLI takes top and says so: top module: top (named by top.xdc), measured apart. Vivado builds the top the project names: a gap until the student names it, no longer a silent wrong

Which error pages explain the messages?

• two-tops: Two or more design modules that nothing instantiates; the CLI does not pick one by file name (Lab 4 folders name the file after the wrong one).

What is the probe's code?

From test/sv/93_two_roots_file_name.

counter.sv

// A lab folder as the course's Vivado projects leave it: one file named after the plain counter, which the
// testbench-less part of the lab simulates, and the board version next to it, which the project names as its
// top. Nothing instantiates either, so both could be the top.
module counter(input logic clk, input logic btnC, output logic [15:0] led);
  always_ff @(posedge clk) if (btnC) led <= 16'd0; else led <= led + 16'd1;
endmodule
// the board version: one step every four clocks (the lab divides the clock further; a clock enable keeps it simple)
module top(input logic clk, input logic btnC, output logic [15:0] led);
  logic [1:0] div;
  always_ff @(posedge clk) div <= btnC ? 2'd0 : div + 2'd1;
  always_ff @(posedge clk)
    if (btnC) led <= 16'd0;
    else if (div == 2'd3) led <= led + 16'd1;
endmodule

tb.sv

module tb;
  logic clk = 0, btnC = 1; logic [15:0] led;
  top dut(.clk(clk), .btnC(btnC), .led(led));
  always #5 clk = ~clk;
  integer i, bad = 0;
  initial begin
    @(posedge clk); #1 btnC = 0;
    for (i = 1; i <= 40; i++) begin
      @(posedge clk); #1;
      if (led !== 16'(i / 4)) begin bad++; if (bad < 4) $display("FAIL: after %0d clocks led=%0d, want %0d", i, led, i / 4); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 40", bad);
    $finish;
  end
endmodule

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