SystemVerilog probes · 92Vivado: supported

a $display debug print left in a clocked design module: if (q == 4'd15) $display("wrapped");

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.239): '$display: Limited Support', and 'Vivado synthesis ignores unsupported system tasks.'

What does the open-source chain do with it?

the CLI drops the print before place and route (delete t:$print in its synthesis script), as Vivado ignores it; dewfpga sim prints 'wrapped' each time the counter wraps, and iverilog warns "System task ($display) cannot be synthesized in an always_ff process."

What is the probe's code?

From test/sv/92_display_in_design.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] q = '0;
  always_ff @(posedge clk) begin
    if (btnC) q <= '0; else q <= q + 4'd1;
    if (q == 4'd15) $display("wrapped");  // a debug print left in the design
  end
  assign led = {sw[15:4], q};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  integer i;
  initial begin
    btnC = 1; tick; btnC = 0;
    for (i = 0; i < 40; i = i + 1) begin
      sw = $urandom; #1
      if (led !== {sw[15:4], 4'(i)}) begin $display("FAIL: after %0d edges sw=%h led=%h", i, sw, led); $finish; end
      tick;
    end
    $display("PASS"); $finish;
  end
endmodule

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