SystemVerilog probes · 91Vivado: supported

a design split over two files: top in design.sv, its submodule counter in counter.sv (the usual lab layout)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 'Compilation Units' (p.270): 'A compilation unit is a collection of one or more SV source files compiled together', and its Tcl flow reads one file per command (read_verilog {test1.sv}, read_verilog {test2.sv}, read_verilog test3.sv)

What does the open-source chain do with it?

dewfpga sim and bit find the top from the hierarchy ('top module: top') and hand both files to each tool. It is the only probe whose design files all reach sim and bit, so it is the one that sees sim or bit drop a file

What is the probe's code?

From test/sv/91_submodule_own_file.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] q;
  counter u_c (.clk(clk), .rst(btnC), .q(q));   // the submodule lives in counter.sv
  assign led = {sw[15:4], sw[3:0] ^ q};
endmodule

counter.sv

module counter(input logic clk, input logic rst, output logic [3:0] q);
  always_ff @(posedge clk) if (rst) q <= '0; else q <= q + 4'd1;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  integer i;
  initial begin
    btnC = 1; tick; btnC = 0;
    for (i = 0; i < 40; i = i + 1) begin
      sw = $urandom; #1
      if (led !== {sw[15:4], sw[3:0] ^ 4'(i)}) begin $display("FAIL: after %0d edges sw=%h led=%h", i, sw, led); $finish; end
      tick;
    end
    $display("PASS"); $finish;
  end
endmodule

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