SystemVerilog probes · 90Vivado: supported

a parameter check in an initial block: initial if (N < 8) $warning(...)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.286): '$error, $warning, $info: Supported only within initial blocks, and can only be used to evaluate constant expressions; for example, parameters.'; Ch.9 Table 21 (p.241): '$warning: Supported', '$info: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/90_elab_warning_initial.

design.sv

module top #(parameter int N = 4) (input logic [15:0] sw, output logic [15:0] led);
  initial if (N < 8) $warning("top: N = %0d, only the low switches are used", N);   // a parameter check
  assign led = sw & 16'((1 << N) - 1);
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (led !== (sw & 16'h000f)) begin $display("FAIL: sw=%h led=%h, want %h", sw, led, sw & 16'h000f); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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