the guide · 7.1How do you run CS223 labs on a Mac without Vivado?

Which course file breaks?

Two. One is fixed for you: SevSeg_4digit.sv (also handed out as SevenSegmentDisplay.sv), as source code, has a port line that Vivado and Icarus accept and Yosys does not (port-neither-input-nor-output). The other is not fixed yet: the ready modules the course hands out in netlist form (LUT primitives, \<const0>, (* keep_hierarchy *)), SevSeg_4digit.sv among them, build in Vivado, but the CLI takes them for a netlist Vivado left behind and stops sim and bit with "Delete it from this folder". 5 of the 89 folders measured from old student repos hold such a module: 4 are one repo's copy of the course's handout folder (its example projects and ready modules), 1 is a student's project that copied the modules in.

output [6:0]seg, logic dp,     // dp inherits `output` from the previous port, per the standard

Yosys does not implement that inheritance. dewfpga bit supplies the direction in a temporary compiler copy before synthesis and tells you so. Your saved file is unchanged:

SevSeg_4digit.sv:4: note [port-neither-input-nor-output]: wrote the port direction in:  output [6:0]seg, output logic dp,   (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both)

The original file is preserved, so it remains available to other tools exactly as you wrote it. The fix misses the line when a comment sits between seg, and logic dp (at the end of the seg, line, on a line of its own, or a /* */ between the two), or when a comment in the port list holds a ;; then Yosys stops with Module port `\dp' is neither input nor output. and no fix, so move the comment out of the way. More things Vivado lets through and Yosys refuses came up in old student repos. One more port-line shape is fixed the same way, by bit; the rest stop the build and name the line, except where the item says otherwise:

• An instance without a name, trans_3s_clock(clk, reset, out);. The standard requires a name: trans_3s_clock u1(clk, reset, out);.
• A latch in an always_comb block: a signal not assigned on every path (an if without else, a case without default). Vivado builds a latch and warns; Yosys refuses. Give the signal a default value at the top of the block.
• A port list where a later port only has a range, input logic [7:0] d, [2:0] s: bit writes the direction in, like the seven-segment line above; sim does not. When such an output is written in an always block (output logic [6:0] seg, [3:0] an), sim stops with "'an' is not a valid l-value" until a bit has rewritten the line.
• A reset branch that loads a signal, not a constant, in an always_ff with posedge reset: the bitstream is built with Yosys warnings only, and while the reset is held the board does not do what sim shows. A register written on both clock edges stops the build, with no line number.
• An asynchronous reset ORed with a synchronous clear, always_ff @(posedge clk, posedge reset) if (reset || clear): the build stops with "Multiple edge sensitive events found for this signal!", no line number, and advice about two always blocks that does not fit one.
• A statement after the reset's if/else in an always_ff with an asynchronous reset: the build stops with "Async reset ... yields non-constant value", no line number, and advice about the reset branch.
• A file Vivado wrote after synthesis (\<const0>, keep_hierarchy) copied in as if it were source: the build stops, names the file and says to delete it. The same check also stops the course's netlist-form modules above, and a module with UG901's own (* keep_hierarchy = "yes" *) attribute.

What else was tried: four modules from old student repos, together in one design. An FSM with typedef enum, a 16x8 RAM, a debouncer and the seven-segment driver above: 136 LUTs, 48 flip-flops, timing passes at 154.70 MHz against the 100 MHz clock, bitstream in 4.5 seconds. Language features in those files that both Icarus (sim) and Yosys (bit) accepted: parameter, generate, struct packed, $clog2, unique case, packed arrays, interface with modport (Icarus 13 accepts one only while no module port is typed with it; a port like sum_if.prod bus fails sim and builds in bit). A submodule file named differently from its module, Turkish characters in comments, and spaces in the folder path went through too. A file saved as "UTF-8 with BOM" stops the build, with the command that removes the mark. That is four files, not the whole course.

7. Which errors does the CLI stop with, and what do they mean?

When sim, bit or flash stops, it prints one message in one format:

blink.sv:12: ERROR [code]: what is wrong, in one line
  Fix: what to change
  https://nosey-dewdrop.github.io/dewfpga/errors/code/

blink.sv:12 is the line in your file, not in a copy the tool made. code names the entry in the error catalog; the page behind the address holds what you saw, why it happens, the fix and an example line. Warnings and notes carry the same code in the same brackets, without the stop. The catalog, every code on one page: Which error did you get? It is generated from one file, docs/errors.md, by docs/errors-build.sh.

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The commands this section names: dewfpga bit
Every SystemVerilog construct measured so far, next to what Vivado does: the probes, stage by stage

Stuck on an error? Every error from this setup, filed under the exact line it printed.