SystemVerilog probes · 16bVivado: supported

'return expr;' inside a function

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Return values and void functions: Supported' (the same table lists 'Jump statements: Not Recommended', not Not Supported)

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 7 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/16b_func_return.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  function automatic logic [3:0] maxn(input logic [3:0] a, input logic [3:0] b);
    if (a > b) return a;
    return b;
  endfunction
  assign led[3:0] = maxn(sw[3:0], sw[7:4]);
  assign led[15:4] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0029; #1
    if (!(led === 16'h0009)) begin $display("FAIL: return a (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h00B2; #1
    if (!(led === 16'h000B)) begin $display("FAIL: return b (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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