SystemVerilog probes · 16Vivado: supported

function automatic with a loop, plain function, task automatic called in always_comb

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Static and Automatic task', 'Static and Automatic function': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/16_func_task.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  function automatic logic [4:0] popcount(input logic [15:0] v);
    popcount = '0;
    for (int i = 0; i < 16; i = i + 1) popcount = popcount + v[i];
  endfunction
  function logic [3:0] rev4(input logic [3:0] v);
    rev4 = {v[0], v[1], v[2], v[3]};
  endfunction
  task automatic invert(input logic [3:0] a, output logic [3:0] y);
    y = ~a;
  endtask
  always_comb begin
    led[4:0] = popcount(sw);
    led[8:5] = rev4(sw[3:0]);
    invert(sw[7:4], led[12:9]);
    led[15:13] = '0;
  end
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'hF0A3; #1
    if (!(led[4:0] === 5'd8 && led[8:5] === 4'hC && led[12:9] === 4'h5 && led[15:13] === 3'd0)) begin $display("FAIL: function/task results (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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