SystemVerilog probes · 15Vivado: supported

generate for with genvar (named block), for (genvar j..) with if-generate, case-generate

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Generate constructs: Supported'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/15_generate.

design.sv

module top #(parameter bit USE_XOR = 1) (input logic [15:0] sw, output logic [15:0] led);
  genvar i;
  generate
    for (i = 0; i < 4; i = i + 1) begin : g_and
      assign led[i] = sw[i] & sw[i+4];
    end
  endgenerate
  for (genvar j = 0; j < 4; j++) begin : g_sel
    if (USE_XOR) begin : g_x
      assign led[4+j] = sw[j] ^ sw[j+4];
    end else begin : g_o
      assign led[4+j] = sw[j] | sw[j+4];
    end
  end
  localparam int MODE = 2;
  case (MODE)
    1:       begin : c1 assign led[15:8] = 8'h11;    end
    2:       begin : c2 assign led[15:8] = sw[15:8]; end
    default: begin : cd assign led[15:8] = '0;       end
  endcase
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0F6A; #1
    if (!(led === 16'h0FC2)) begin $display("FAIL: generate for/if/case (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: typed parameters, one depending on another, localparam, #(.W(8),.K(3)) and positional #(4)
next: function automatic with a loop, plain function, task automatic called in always_comb